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integrated circuit systems, inc. ics950211 0465e?05/17/05 block diagram pin configuration recommended application: brookdale and brookdale -g chipset with p4 processor. output features: 3 - pairs of differential cpu clocks (differential current mode) 5 - 3v66 @ 3.3v 10 - pci @ 3.3v 2 - 48mhz @ 3.3v fixed 1 - ref @ 3.3v, 14.318mhz 1 - vch/3v66 @ 3.3v, 48 mhz or 66.6 mhz features/benefits: programmable output frequency. programmable output divider ratios. programmable output rise/fall time. programmable output skew. programmable spread percentage for emi control. watchdog timer technology to reset system if system malfunctions. programmable watch dog safe frequency. support i 2 c index read/write and block read/write operations. uses external 14.318mhz crystal. key specifications: ? cpu output jitter <150ps 3v66 output jitter <250ps cpu output skew <100ps programmable timing control hub? for p4? 1. these outputs have 2x drive strength. * internal pull-up resistor of 120k to vdd ** these inputs have 120k internal pull-down to gnd 56-pin 300-mil ssop & 240-mil tssop power groups vdda = analog core pll vddref = ref, xtal avdd48 = 48mhz frequency table for additional frequency selections please refer to byte 0. * for 950211bf version, this frequency is 166.66mhz. 4 s f3 s f2 s f1 s f0 s f k l c u p c z h m 6 6 v 3 z h m k l c i c p z h m 00000 * 6 6 . 6 66 6 . 6 63 3 . 3 3 0000 1 0 0 . 0 0 16 6 . 6 63 3 . 3 3 00010 0 0 . 0 0 26 6 . 6 63 3 . 3 3 00011 3 3 . 3 3 16 6 . 6 63 3 . 3 3 00 100 0 9 . 0 0 17 2 . 7 63 6 . 3 3 00 10 1 0 0 . 5 0 10 0 . 0 70 0 . 5 3 00 110 0 0 . 9 0 17 6 . 2 73 3 . 6 3 00 111 0 0 . 4 1 10 0 . 6 70 0 . 8 3 01000 0 0 . 7 1 10 0 . 8 70 0 . 9 3 01001 0 0 . 7 2 16 8 . 2 73 4 . 6 3 01010 0 0 . 0 3 19 2 . 4 74 1 . 7 3 01011 0 5 . 2 3 11 7 . 5 79 8 . 7 3 01100 0 0 . 5 0 20 0 . 0 70 0 . 5 3 01101 0 0 . 0 7 17 6 . 6 53 3 . 8 2 01110 0 0 . 0 8 10 0 . 0 60 0 . 0 3 01111 0 0 . 0 9 13 3 . 3 67 6 . 1 3 pll2 pll1 spread spectr um 48mhz_usb pciclk (6:0) 3v66 (5:2, 0) 48mhz_dot 3v66_1/vch_clk x1 x2 xtal osc cpu divder pci divder 3v66 divder wden pd# cpu_stop# pci_stop# multsel0 s data sclk vtt_pwrgd# fs (4:0) i ref control logic config. reg. ref 3 3 7 5 3 cpuclkt (2:0) cpuclkc (2:0) pciclk_f (2:0) stop stop vddref x1 x2 gnd pciclk_f0 pciclk_f1 pciclk_f2 vddpci gnd *wden/pciclk0 pciclk1 pciclk2 pciclk3 vddpci gnd pciclk4 pciclk5 pciclk6 vdd3v66 gnd 3v66_2 3v66_3 3v66_4 3v66_5 # vdda gnd *vtt_pwrgd# 1 1 1 *pd ref fs1 fs0 cpu_stop#* cpuclkt0 cpuclkc0 vddcpu cpuclkt1 cpuclkc1 gnd vddcpu cpuclkt2 cpuclkc2 multsel0* i ref gnd fs2 48mhz_usb/fs3** 48mhz_dot avdd48 gnd 3v66_1/vch_clk/fs4** pci_stop#* 3v66_0 vdd gnd sclk s data 1 ics950211 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 9 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 4 9 48 47 46 45 44 43 42 41 40 3 9 38 37 36 35 34 33 32 31 30 2 9
2 integrated circuit systems, inc. ics950211 0465e?05/17/05 pin description the ics950211 is a single chip clock solution for desktop designs using the intel brookdale chipset with pc133 or ddr memory. it provides all necessary clock signals for such a system. the ics950211 is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). this part incorporates ics's newest clock technology which offers more robust features and functionality. employing the use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. m/n control can configure output frequency with resolution up to 0.1mhz increment. general description r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d , 9 1 , 4 1 , 8 , 1 0 5 , 6 4 , 2 3 d d vr w p. y l p p u s r e w o p v 3 . 3 21 xn i . 2 x m o r f r o t s i s e r k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 32 xt u o . ) f p 3 3 ( p a c d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c , 1 3 , 7 2 , 0 2 , 5 1 , 9 , 4 7 4 , 1 4 , 6 3 d n gr w p. y l p p u s v 3 . 3 r o f s n i p d n u o r g 3 3 , 1 2 , 2 2 , 3 2 , 4 2) 0 , 2 : 5 ( 6 6 v 3t u o. b u h r o f s t u p t u o k c o l c z h m 6 6 d e x i f v 3 . 3 5 , 6 , 7) 0 : 2 ( f _ k l c i c pt u ot u p t u o k c o l c i c p v 3 . 3 0 1 n e d wn i. h g i h d e h c t a l n e h w d e l b a n e . t i u c r i c g o d h c t a w f o e l b a n e e r a w d r a h 0 k l c i c pt u o. t u p t u o k c o l c i c p v 3 . 3 1 1 , 2 1 , 3 1 , 6 1 , 7 1 , 8 1) 1 : 6 ( k l c i c pt u o. s t u p t u o k c o l c i c p v 3 . 3 5 2# d pn i w o l a o t n i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a e r a l a t s y r c e h t d n a o c v e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p . s m 3 n a h t r e t a e r g e b t o n l l i w n w o d r e w o p e h t f o y c n e t a l e h t . d e p p o t s 6 2a d d vr w p. v 3 . 3 r e w o p g o l a n a 8 2# d g r w p _ t t vn i ) 0 : 4 ( s f n e h w e n i m r e t e d o t d e s u e b o r t s e v i t i s n e s l e v e l a s i t u p n i l t t v l v 3 . 3 s i h t . ) w o l e v i t c a ( d e l p m a s e b o t y d a e r e r a d n a d i l a v e r a s t u p n i 0 3k l c sn ii r o f n i p k c o l c 2 . t n a r e l o t v 5 y r t i u c r i c c 9 2a t a d so / ii r o f n i p a t a d 2 . t n a r e l o t v 5 y r t i u c r i c c 4 3# p o t s _ i c pn i e r a h c i h w f _ k l c i c p t p e c x e w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c k l c i c p s t l a h . g n i n n u r e e r f 5 3 k l c _ h c v / 1 _ 6 6 v 3t u o h g u o r h t e l b a t c e l e s t u p t u o v 3 . 3i 2 cr o o c v l a n r e t n i m o r f z h m 6 6 e b o t . ) c s s - n o n ( z h m 8 4 4 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 7 38 4 d d v ar w p. v 3 . 3 r e w o p g o l a n a 8 3t o d _ z h m 8 4t u o. t o d r o f t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 9 3 3 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l b s u _ z h m 8 4t u o. b s u r o f t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 2 4f e r it u o s e r i u q e r n i p s i h t . s r i a p k l c u p c e h t r o f t n e r r u c e c n e r e f e r e h t s e h s i l b a t s e n i p s i h t e t a i r p o r p p a e h t h s i l b a t s e o t r e d r o n i d n u o r g o t d e i t r o t s i s e r n o i s i c e r p d e x i f a . t n e r r u c 3 40 l e s t l u mn i s t u p t u o u p c r o f r e i l p i t l u m t n e r r u c e h t g n i t c e l e s r o f t u p n i l t t v l v 3 . 3 1 5 , 8 4 , 4 4) 0 : 2 ( c k l c u p ct u o t n e r r u c e r a e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " y r o t n e m e l p m o c " . s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e d n a s t u p t u o 2 5 , 9 4 , 5 4) 0 : 2 ( t k l c u p ct u o d n a s t u p t u o t n e r r u c e r a e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " e u r t " . s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e 4 5 , 5 5 , 0 4) 0 : 2 ( s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 3 5# p o t s _ u p cn i h c i h w f _ k l c u p c t p e c x e w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c k l c u p c s t l a h . g n i n n u r e e r f e r a 6 5f e rt u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3
3 integrated circuit systems, inc. ics950211 0465e?05/17/05 maximum allowed current n o i t i d n o c n o i t p m u s n o c y l p p u s v 3 . 3 x a m , s d a o l p a c e t e r c s i d x a m v 5 6 4 . 3 = d d v d n g r o d d v = s t u p n i c i t a t s l l a e d o m n w o d r e w o p ) 0 = # n w d r w p ( a m 0 4 e v i t c a l l u f a m 0 6 3 host swing select functions 0 l e s i t l u m t e g r a t d r a o b z m r e t / e c a r t , r e c n e r e f e r = f e r i v d d ) r r * 3 ( / t u p t u o t n e r r u c z @ h o v 0s m h o 0 5 , % 1 1 2 2 = r r a m 0 0 . 5 = f e r i f e r i * 4 = h o i0 5 @ v 0 . 1 1s m h o 0 5 , % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 6 = h o i0 5 @ v 7 . 0
4 integrated circuit systems, inc. ics950211 0465e?05/17/05 general i 2 c serial interface information how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit *see notes on the following page . ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n a c k a c k data byte count = x a c k ics (slave/receiver) controller (host) x byte a ck a ck
5 integrated circuit systems, inc. ics950211 0465e?05/17/05 byte 0: functionality and frequency select register (default=0) notes: 1. default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. 2. for 950211bf version, this frequency is 166.66mhz. t i bn o i t p i r c s e dd w p t i b ) 4 : 7 , 2 ( 2 t i b7 t i b6 t i b5 t i b4 t i b k l c u p c z h m 6 6 v 3 z h m k l c i c p z h m % d a e r p s 1 e t o n 4 s f3 s f2 s f1 s f0 s f 00000 6 6 . 6 6 2 6 6 . 6 63 3 . 3 3d a e r p s n w o d % 5 . 0 - o t 0 0000 1 0 0 . 0 0 16 6 . 6 63 3 . 3 3d a e r p s n w o d % 5 . 0 - o t 0 00010 0 0 . 0 0 26 6 . 6 63 3 . 3 3d a e r p s n w o d % 5 . 0 - o t 0 00011 3 3 . 3 3 16 6 . 6 63 3 . 3 3d a e r p s n w o d % 5 . 0 - o t 0 00 100 0 9 . 0 0 17 2 . 7 63 6 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 00 10 1 0 0 . 5 0 10 0 . 0 70 0 . 5 3d a e r p s r e t n e c % 5 3 . 0 - / + 00 110 0 0 . 9 0 17 6 . 2 73 3 . 6 3d a e r p s r e t n e c % 5 3 . 0 - / + 00 111 0 0 . 4 1 10 0 . 6 70 0 . 8 3d a e r p s r e t n e c % 5 3 . 0 - / + 01000 0 0 . 7 1 10 0 . 8 70 0 . 9 3d a e r p s r e t n e c % 5 3 . 0 - / + 01001 0 0 . 7 2 16 8 . 2 73 4 . 6 3d a e r p s r e t n e c % 5 3 . 0 - / + 01010 0 0 . 0 3 19 2 . 4 74 1 . 7 3d a e r p s r e t n e c % 5 3 . 0 - / + 01011 0 5 . 2 3 11 7 . 5 79 8 . 7 3d a e r p s r e t n e c % 5 3 . 0 - / + 01100 0 0 . 5 0 20 0 . 0 70 0 . 5 3d a e r p s r e t n e c % 5 3 . 0 - / + 01101 0 0 . 0 7 17 6 . 6 53 3 . 8 2d a e r p s r e t n e c % 5 3 . 0 - / + 01110 0 0 . 0 8 10 0 . 0 60 0 . 0 3d a e r p s r e t n e c % 5 3 . 0 - / + 01111 0 0 . 0 9 13 3 . 3 67 6 . 1 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 00 0 0 9 . 3 3 15 9 . 6 68 4 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 00 1 3 3 . 3 3 17 6 . 6 63 3 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 0 10 0 0 . 0 2 10 0 . 0 60 0 . 0 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 0 1 1 0 0 . 5 2 10 5 . 2 65 2 . 1 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 10 0 0 9 . 4 3 15 4 . 7 63 7 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 10 1 0 0 . 7 3 10 5 . 8 65 2 . 4 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 110 0 0 . 9 3 10 5 . 9 65 7 . 4 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 11 1 0 0 . 1 4 10 5 . 0 75 2 . 5 3d a e r p s r e t n e c % 5 3 . 0 - / + 11000 0 0 . 3 4 10 5 . 1 75 7 . 5 3d a e r p s r e t n e c % 5 3 . 0 - / + 1100 1 0 0 . 5 4 10 5 . 2 75 2 . 6 3d a e r p s r e t n e c % 5 3 . 0 - / + 11010 0 0 . 0 5 10 0 . 5 70 5 . 7 3d a e r p s r e t n e c % 5 3 . 0 - / + 11011 0 0 . 5 5 10 5 . 7 75 7 . 8 3d a e r p s r e t n e c % 5 3 . 0 - / + 11100 0 0 . 0 6 10 0 . 0 80 0 . 0 4d a e r p s r e t n e c % 5 3 . 0 - / + 1110 1 0 0 . 0 5 19 2 . 4 64 1 . 2 3d a e r p s r e t n e c % 5 3 . 0 - / + 11110 0 0 . 0 6 17 5 . 8 69 2 . 4 3d a e r p s r e t n e c % 5 3 . 0 - / + 11111 0 0 . 0 7 16 8 . 2 73 4 . 6 3d a e r p s r e t n e c % 5 3 . 0 - / + 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b s t u p n i h c t a l y b d e t c e l e s e b l l i w y c n e u q e r f e f a s g o d h c t a w - 0 ) 0 : 4 ( t i b 0 1 e t y b y b d e m m a r g o r p e b l l i w y c n e u q e r f e f a s g o d h c t a w - 1 0
6 integrated circuit systems, inc. ics950211 0465e?05/17/05 byte 1: output control register (1 = enable, 0 = disable) byte 3: output control register (1 = enable, 0 = disable) byte 2: output control register (1 = enable, 0 = disable) byte 4: output control register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b8 31 t o d _ z h m 8 4 6 t i b9 31 b s u _ z h m 8 4 5 t i b-1 e l b a s i d = 0 , e l b a n e = 1 t c e t e d t f i h s r a e g t e s e r 4 t i b-0 ) e l b a t l o r t n o c . q e r f c n y s a e e s ( 0 t i b l o r t n o c . q e r f c n y s a 3 t i b5 30 , k l c _ h c v / 1 _ 6 6 v 3z h m 8 4 = 1 , z h m 6 6 . 6 6 = ) t l u a f e d ( 2 t i b71 2 f _ k l c i c p 1 t i b61 1 f _ k l c i c p 0 t i b51 0 f _ k l c i c p t i b# n i pd w pn o i t p i r c s e d 7 t i b5 4 , 4 41 2 c / t u p c 6 t i b9 4 , 8 41 1 c / t u p c 5 t i b2 5 , 1 51 0 c / t u p c 4 t i b-x k c a b d a e r 4 s f 3 t i b-x k c a b d a e r 3 s f 2 t i b-x k c a b d a e r 2 s f 1 t i b-x k c a b d a e r 1 s f 0 t i b-x k c a b d a e r 0 s f t i b# n i pd w pn o i t p i r c s e d 7 t i b-x ) k c a b d a e r ( l e s t l u m 6 t i b8 11 6 _ k l c i c p 5 t i b7 11 5 _ k l c i c p 4 t i b6 11 4 _ k l c i c p 3 t i b3 11 3 _ k l c i c p 2 t i b2 11 2 _ k l c i c p 1 t i b1 11 1 _ k l c i c p 0 t i b0 11 0 _ k l c i c p notes: 1. pwd = power on default 2. for disabled clocks, they stop low for single ended clocks. differential cpu clocks stop with cpuclkt at high, cpuclkc off, and external resistor termination will bring cpuclkc low. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) e l b a t l o r t n o c . q e r f . c n y s a e e s ( 1 t i b l o r t n o c . q e r f . c n y s a 6 t i b-x d e v r e s e r 5 t i b3 31 0 _ 6 6 v 3 4 t i b5 31 k l c _ h c v / 1 _ 6 6 v 3 3 t i b4 21 5 _ 6 6 v 3 2 t i b3 21 4 _ 6 6 v 3 1 t i b2 21 3 _ 6 6 v 3 0 t i b1 21 2 _ 6 6 v 3
7 integrated circuit systems, inc. ics950211 0465e?05/17/05 byte 7: revision id and device id register byte 5: programming edge rate (1 = enable, 0 = disable) byte 6: vendor id register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i bx1 * e l b a p p o t s = 1 ; g n i n n u r e e r f = 0 , l o r t n o c g n i n n u r e e r f 0 c / t k l c u p c 6 t i bx1 * e l b a p p o t s = 1 ; g n i n n u r e e r f = 0 , l o r t n o c g n i n n u r e e r f 1 c / t k l c u p c 5 t i bx1 * e l b a p p o t s = 1 ; g n i n n u r e e r f = 0 , l o r t n o c g n i n n u r e e r f 2 c / t k l c u p c 4 t i bx1 ) d e v r e s e r ( 3 t i bx1 ) d e v r e s e r ( 2 t i bx1 ) d e v r e s e r ( 1 t i bx1 ) d e v r e s e r ( 0 t i bx1 ) d e v r e s e r ( t i be m a nd w pn o i t p i r c s e d 7 t i b7 d i e c i v e d0 e c i v e d l a u d i v i d n i n o d e s a b e b l l i w s e u l a v d i e c i v e d . e s a c s i h t n i " h 1 0 " 6 t i b6 d i e c i v e d0 5 t i b5 d i e c i v e d0 4 t i b4 d i e c i v e d0 3 t i b3 d i e c i v e d0 2 t i b2 d i e c i v e d0 1 t i b1 d i e c i v e d0 0 t i b0 d i e c i v e d1 t i be m a nd w pn o i t p i r c s e d 7 t i b3 t i b d i n o i s i v e rx n o i s i v e r s ' e c i v e d l a u d i v i d n i n o d e s a b e b l l i w s e u l a v d i n o i s i v e r 6 t i b2 t i b d i n o i s i v e rx 5 t i b1 t i b d i n o i s i v e rx 4 t i b0 t i b d i n o i s i v e rx 3 t i b3 t i b d i r o d n e v0) d e v r e s e r ( 2 t i b2 t i b d i r o d n e v0) d e v r e s e r ( 1 t i b1 t i b d i r o d n e v0) d e v r e s e r ( 0 t i b0 t i b d i r o d n e v1) d e v r e s e r ( asynchronous frequency control table byte 4 byte 3 3v66 [0:3] pci_f [1:2] pcick [0:6] note bit 7 bit 4 0 0 66.01 mhz 33.005 mhz from fix pll (no spread) 0 1 75.44 mhz 37.72 mhz from fix pll (no spread) 1 0 66.66 mhz 33.33 mhz from main pll (default) 1 1 88.01 mhz 44.005 mhz from fix pll (no spread) * this functionality is only available in bf version.
8 integrated circuit systems, inc. ics950211 0465e?05/17/05 byte 10: programming enable bit 8 watchdog control register byte 11: vco frequency m divider (reference divider) control register byte 9: watchdog timer count register t i be m a nd w pn o i t p i r c s e d 7 t i b7 d w0 ? x o t d n o p s e r r o c s t i b 8 e s e h t f o n o i t a t n e s e r p e r l a m i c e d e h t e d o m m r a l a o t s e o g t i e r o f e b t i a w l l i w r e m i t g o d h c t a w e h t s m 0 9 2 s i p u r e w o p t a t l u a f e d . g n i t t e s e f a s e h t o t y c n e u q e r f e h t t e s e r d n a . s d n o c e s 3 . 2 = s m 0 9 2 ? 8 6 t i b6 d w0 5 t i b5 d w0 4 t i b4 d w0 3 t i b3 d w1 2 t i b2 d w0 1 t i b1 d w0 0 t i b0 d w0 t i be m a nd w pn o i t p i r c s e d 7 t i b8 v i d nx 8 t i b r e d i v i d n 6 t i b6 v i d mx e h t o t d s o p s e r r o c ) 0 : 6 ( v i d m f o n o i t a t n e s e r p s e r l a m i c e d e h t e h t o t l a u q e s i p u r e w o p t a t l u a f e d . e u l a v r e d i v i d e c n e r e f e r . n o i t c e l e s s t u p n i d e h c t a l 5 t i b5 v i d mx 4 t i b4 v i d mx 3 t i b3 v i d mx 2 t i b2 v i d mx 1 t i b1 v i d mx 0 t i b0 v i d mx t i be m a nd w pn o i t p i r c s e d 7 t i b m a r g o r p e l b a n e 0 t i b e l b a n e g n i m m a r g o r p 1 0 e t y b r o s e h c t a l w h y b d e t c e l e s e r a s e i c n e u q e r f . g n i m m a r g o r p o n = 0 i l l a e l b a n e = 2 . g n i m a r g o r p c 6 t i be l b a n e d w0 . t i b e l b a n e g o d h c t a w . e l b a n e = 1 , e l b a s i d = 0 . e u l a v d e h c t a l n e d w e t i r w r e v o l l i w t i b s i h t 5 t i bm r a l a d w0 s u t a t s m r a l a = 1 l a m r o n = 0 s u t a t s m r a l a g o d h c t a w 4 t i b4 f s0 e f a s e h t e r u g i f n o c l l i w s t i b e s e h t o t g n i t i r w . s t i b y c n e u q e r f e f a s g o d h c t a w e l b a t 4 : 7 , 2 t i b 0 e t y b o t g n i d n o p s r r o c y c n e u q e r f 3 t i b3 f s0 2 t i b2 f s0 1 t i b1 f s0 0 t i b0 f s0 byte 8: byte count read back register t i be m a nd w pn o i t p i r c s e d 7 t i b7 e t y b0 w o h d n a t n u o c e t y b e r u g i f n o c l l i w r e t s i g e r s i h t o t g n i t i r w : e t o n s i t l u a f e d , k c a b d a e r e b l l i w s e t y b y n a m f 0 h . s e t y b 5 1 = 6 t i b6 e t y b0 5 t i b5 e t y b0 4 t i b4 e t y b0 3 t i b3 e t y b1 2 t i b2 e t y b1 1 t i b1 e t y b1 0 t i b0 e t y b1
9 integrated circuit systems, inc. ics950211 0465e?05/17/05 byte 14: spread spectrum control register byte 15: output divider control register byte 13: spread spectrum control register t i be m a nd w pn o i t p i r c s e d 7 t i b7 s sx d a e r p s e h t m a r g o r p l l i w t i b ) 0 : 2 1 ( m u r t c e p s d a e r p s e h t e h t n o d e s a b d e t a l u c l a c e b o t s d e e n t n e c e r p d a e r p s . e g a t n e c e r p d a e r p s d n a t n u o m a g n i d a e r p s , e l i f o r p g n i d a e r p s , y c n e u q e r f o c v . r e d i v i d s f d e h c t a l s i n o r e w o p t l u a f e d . y c n e u q e r f 6 t i b6 s sx 5 t i b5 s sx 4 t i b4 s sx 3 t i b3 s sx 2 t i b2 s sx 1 t i b1 s sx 0 t i b0 s sx t i be m a nd w pn o i t p i r c s e d 7 t i bd e v r e s e rxd e v r e s e r 6 t i bd e v r e s e rxd e v r e s e r 5 t i bd e v r e s e rxd e v r e s e r 4 t i b2 1 s sx 2 1 t i b m u r t c e p s d a e r p s 3 t i b1 1 s sx 1 1 t i b m u r t c e p s d a e r p s 2 t i b0 1 s sx 0 1 t i b m u r t c e p s d a e r p s 1 t i b9 s sx 9 t i b m u r t c e p s d a e r p s 0 t i b8 s sx 8 t i b m u r t c e p s d a e r p s t i be m a nd w pn o i t p i r c s e d 7 t i b3 v i d u p cx 4 e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c 2 u p c o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t 6 t i b2 v i d u p cx 5 t i b1 v i d u p cx 4 t i b0 v i d u p cx 3 t i b3 v i d u p cx a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c ] 0 : 1 [ u p c r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b 4 e s e h t . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t o t 2 t i b2 v i d u p cx 1 t i b1 v i d u p cx 0 t i b0 v i d u p cx byte 12: vco frequency n divider (vco divider) control register t i be m a nd w pn o i t p i r c s e d 7 t i b7 v i d nx e h t o t d n o p s e r r o c ) 0 : 8 ( v i d n f o n o i t a t n e s e r p e r l a m i c e d e h t e h t o t l a u q e s i p u r e w o p t a t l u a f e d . e u l a v r e d i v i d o c v . 1 1 e t y b n i d e t a c o l s i 8 v i d n e c i t o n . n o t c e l e s s t u p n i d e h c t a l 6 t i b6 v i d nx 5 t i b5 v i d nx 4 t i b4 v i d nx 3 t i b3 v i d nx 2 t i b2 v i d nx 1 t i b1 v i d nx 0 t i b0 v i d nx
10 integrated circuit systems, inc. ics950211 0465e?05/17/05 byte 17: output divider control register byte 18: group skew control register byte 19: group skew control register table 1 table 2 ) 2 : 3 ( v i d 0 01 00 11 1 ) 0 : 1 ( v i d 0 02 /4 /8 /6 1 / 1 03 /6 /2 1 /4 2 / 0 15 /0 1 /0 2 /0 4 / 1 17 /4 1 /8 2 /6 5 / ) 2 : 3 ( v i d 0 01 00 11 1 ) 0 : 1 ( v i d 0 04 /8 /6 1 /2 3 / 1 03 /6 /2 1 /4 2 / 0 15 /0 1 /0 2 /0 4 / 1 17 /4 1 /8 2 /6 5 / t i be m a nd w pn o i t p i r c s e d 7 t i bv n i _ 6 6 v 3x t i b n o i s r e v n i e s a h p ] 2 : 3 [ 6 6 v 3 6 t i bv n i _ 6 6 v 3x t i b n o i s r e v n i e s a h p 6 6 v 3 5 t i bv n i _ u p cx t i b n o i s r e v n i e s a h p 2 k l c u p c 4 t i bv n i _ u p cx t i b n o i s r e v n i e s a h p ] 0 : 1 [ k l c u p c 3 t i bd e v r e s e rx 4 e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c ] 0 : 1 [ 6 6 v 3 . 1 e l b a t o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d 2 t i bd e v r e s e rx 1 t i bd e v r e s e rx 0 t i bd e v r e s e rx t i be m a nd w pn o i t p i r c s e d 7 t i b1 w e k s _ u p c0 o t t c e p s e r h t i w 2 t / c k l c u p c e h t y a l e d s t i b 2 e s e h t ) 0 : 1 ( t / c k l c u p c s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 s p 0 5 2 = 1 0 s p 0 = 0 0 6 t i b0 w e k s _ u p c1 5 t i bd e v r e s e r0d e v r e s e r 4 t i bd e v r e s e r0d e v r e s e r 3 t i b1 w e k s _ u p c0 e h t y a l e d s t i b 2 e s e h t) 0 : 1 ( t / c k l c u p co t t c e p s e r h t i w k c o l c 2 t / c k l c u p c s p 0 5 2 = 1 0 s p 0 = 0 0s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 2 t i b0 w e k s _ u p c1 1 t i bd e v r e s e r0d e v r e s e r 0 t i bd e v r e s e r0d e v r e s e r t i be m a nd w pe c n e u q e s g n i m m a r g o r p 7 t i b l o r t n o c s t i b 4 e s e h t ) 1 : 3 ( 6 6 v 3 - u p c 1 0 000 s p 0d e v r e s e r 6 t i b10100s p 0 5 1d e v r e s e r 5 t i b 1 1 000 s p 0 0 3d e v r e s e r 4 t i b11100s p 0 5 4d e v r e s e r 3 t i b l o r t n o c s t i b 4 e s e h t 0 _ 6 6 v 3 - u p c 11101s p 0 0 6d e v r e s e r 2 t i b11110s p 0 5 7d e v r e s e r 1 t i b 1 1 111 s p 0 0 9d e v r e s e r 0 t i b1d e v r e s e rd e v r e s e r byte 16: output divider control register t i be m a nd w pn o i t p i r c s e d 7 t i b3 v i d i c px a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c ] 2 : 3 [ 6 6 v 3 r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b 4 e s e h t . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t o t 6 t i b2 v i d i c px 5 t i b1 v i d i c px 4 t i b0 v i d i c px 3 t i b3 v i d 6 6 v 3x a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c ] 0 : 1 [ 6 6 v 3 r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b 4 e s e h t . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t o t 2 t i b2 v i d 6 6 v 3x 1 t i b1 v i d 6 6 v 3x 0 t i b0 v i d 6 6 v 3x
11 integrated circuit systems, inc. ics950211 0465e?05/17/05 byte 20: group skew control register byte 21: slew rate control register byte 22: slew rate control register byte 23: slew rate control register t i be m a nd w pn o i t p i r c s e d 7 t i b1 w e l s f e r1 . s t i b l o r t n o c e t a r w e l s k c o l c f e r k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 6 t i b0 w e l s f e r0 5 t i b1 w e l s ) 4 : 6 ( i c p1 . s t i b l o r t n o c e t a r w e l s k c o l c ) 4 : 6 ( i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 4 t i b0 w e l s ) 4 : 6 ( i c p0 3 t i b ) 1 : 3 ( i c p1 w e l s 1 . s t i b l o r t n o c e t a r w e l s k c o l c ) 1 : 3 ( i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 2 t i b ) 1 : 3 ( i c p0 w e l s 0 1 t i b 0 i c p1 w e l s 1 . s t i b l o r t n o c e t a r w e l s k c o l c 0 i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 0 t i b 0 i c p0 w e l s 0 t i be m a nd w pn o i t p i r c s e d 7 t i bd e v r e s e rx d e v r e s e r 6 t i bd e v r e s e rx 5 t i b1 w e l s h c v1 . s t i b l o r t n o c e t a r w e l s k c o l c h c v k k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 4 t i b0 w e l s h c v0 3 t i b1 w e l s b s u 8 41 . s t i b l o r t n o c e t a r w e l s k c o l c b s u 8 4 k k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 2 t i b0 w e l s b s u 8 40 1 t i b1 w e l s t o d 8 41 . s t i b l o r t n o c e t a r w e l s k c o l c t o d 8 4 k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 0 t i b0 w e l s t o d 8 40 t i be m a nd w pn o i t p i r c s e d 7 t i b1 w e l s f i c p1 . s t i b l o r t n o c e t a r w e l s k c o l c ) 0 : 1 ( 2 f i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 6 t i b0 w e l s f i c p0 . s t i b l o r t n o c e t a r w e l s k c o l c ) 0 : 1 ( 1 f i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 5 t i b1 w e l s f i c p1 . s t i b l o r t n o c e t a r w e l s k c o l c ) 0 : 1 ( f i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 4 t i b0 w e l s f i c p0 3 t i b1 w e l s _ ) 2 : 3 ( 6 6 v 31 . s t i b l o r t n o c e t a r w e l s k c o l c ) 2 : 3 ( 6 6 v 3 k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 2 t i b1 w e l s _ ) 2 : 3 ( 6 6 v 30 1 t i b1 w e l s _ ) 0 : 1 ( 6 6 v 31 . s t i b l o r t n o c e t a r w e l s k c o l c ) 0 : 1 ( 6 6 v 3 k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 0 t i b0 w e l s _ ) 0 : 1 ( 6 6 v 30 t i be m a nd w pe c n e u q e s g n i m m a r g o r p 7 t i b l o r t n o c s t i b 4 e s e h t ) 0 : 6 ( i c p - u p c 1 0 000 s p 0d e v r e s e r 6 t i b10100s p 0 5 1d e v r e s e r 5 t i b 1 1 000 s p 0 0 3d e v r e s e r 4 t i b11100s p 0 5 4d e v r e s e r 3 t i b l o r t n o c s t i b 4 e s e h t ) 0 : 1 ( f i c p - u p c 11101s p 0 0 6d e v r e s e r 2 t i b11110s p 0 5 7d e v r e s e r 1 t i b 1 1 111 s p 0 0 9d e v r e s e r 0 t i b1d e v r e s e rd e v r e s e r
12 integrated circuit systems, inc. ics950211 0465e?05/17/05 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v + 5% parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd -5 5 ma input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 ma input low current i il2 v in = 0 v; inputs with pull-up resistors -200 ma operating c l = 0 pf; select @ 66m 100 ma supply current c l = full load 360 ma iref=2.32 25 ma iref= 5ma 45 ma input frequency f i v dd = 3.3 v; 14.318 mhz pin inductance l p in 7nh c in logic inputs 5 pf c out out put pin capacitance 6 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms t pzh ,t pzh output enable delay (all outputs) 1 10 ns t plz ,t pzh output disable delay (all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. input capacitance 1 delay i dd3.3op power down supply current i dd3.3pd
13 integrated circuit systems, inc. ics950211 0465e?05/17/05 electrical characteristics - pciclk t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f0 1 33.33 mhz output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i o l = 1 ma 0.55 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -33 -33 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.52 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.45 2 ns duty cycle d t1 1 v t = 1.5 v 45 51.5 55 % skew t sk1 1 v t = 1.5 v 155 500 ps jitter t jcyc-cyc 1 v t = 1.5 v 123 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - cpuclk t a = 0 - 70c; v dd = 3.3 v +/-5%; (unless otherwise stated) parameter symbol conditions min typ max units current source output impedance z o v o = v x 3000 ? output high voltage v oh 0.71 1.2 v output high current i oh -13.92 ma rise time 1 t r v ol = 20%, v oh = 80% 175 700 ps differential crossover voltage 1 v x note 3 455055% duty cycle 1 d t v t = 50% 45 49.4 55 % skew 1 , cpu to cpu t sk v t = 50% 40 100 ps jitter, cycle-to-cycle 1 t jcyc-cyc v t = v x 90 150 ps notes: 1 - guaranteed by design, not 100% tested in production. v r = 475w + 1%; iref = 2.32ma; i oh = 6*iref
14 integrated circuit systems, inc. ics950211 0465e?05/17/05 electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o1 66.66 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i o l = 1 ma 0.4 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -33 -33 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 30 38 ma rise time t r1 1 v o l = 0.4 v, v oh = 2.4 v 0.5 3 2 ns fall time t f1 1 v oh = 2.4 v, v o l = 0.4 v 0.5 1.3 2 ns duty cycle d t1 1 v t = 1.5 v 455255% skew t sk1 1 v t = 1.5 v 155 500 ps jitter tjcyc-cyc 1 v t = 1.5 v 150 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - vch, 48mhz dot, 48mhz, usb t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o 1 v o = v dd *(0.5) 48 mhz output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i o l = 1 ma 0.55 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -29 -23 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 29 27 ma 48dot rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 0.6 1 ns 48dot fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 0.7 1 ns vch 48 usb rise time t r 1 v ol = 0.4 v, v oh = 2.4 v 1 1.1 2 ns vch 48 usb fall time tf 1 v oh = 2.4 v, v ol = 0.4 v 1 1.2 2 ns 48 dot to 48 usb skew tskew 1 vt=1.5v 1 ns duty cycle d t1 1 v t = 1.5 v 45 50.1 55 % jitter t jcyc-cyc 1 v t = 1.5 v 130 350 ps 1 guaranteed by design, not 100% tested in production.
15 integrated circuit systems, inc. ics950211 0465e?05/17/05 electrical characteristics - ref t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =10-20 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i o l = 1 ma 0.4 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -29 -23 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 4 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 4 ns duty cycle d t1 1 v t = 1.5 v 455355% jitter t jcyc-cyc v t = 1.5 v 500 ps 1 guaranteed by design, not 100% tested in production.
16 integrated circuit systems, inc. ics950211 0465e?05/17/05 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
17 integrated circuit systems, inc. ics950211 0465e?05/17/05 all 3v66 clocks are to be in pphase with each other. in the case where 3v66_1 is configured as 48mhz vch clock, there is no defined phase relationship between 3v66_1/vch and other 3v66 clocks. the pci group should lag 3v66 by the standard skew described below as tpci. un-buffered mode 3v66 & pci phase relationship 3v66 pciclk_f and pciclk tpci group skews at common transition edges: (un-buffered mode) group symbol conditions min typ max units 3v66 3v66 3v66 pin to pin skew 0 155 500 ps pci pci pci_f and pci pin to pin skew 0 302 500 ps 3v66 to pci s 3v66-pci 3v66 leads 33mhz pci 1.5 1.7 3.5 ns 1 guaranteed by design, not 100% tested in production. pd# functionality # p o t s _ u p ct u p cc u p c6 6 v 3t u o _ z h m 6 6 f _ k l c i c p k l c i c p k l c i c p t o d / b s u z h m 8 4 1l a m r o nl a m r o nz h m 6 6n i _ z h m 6 6n i _ z h m 6 6n i _ z h m 6 6z h m 8 4 0t l u m * f e r it a o l fw o lw o lw o lw o lw o l
18 integrated circuit systems, inc. ics950211 0465e?05/17/05 the impact of asserting the pci_stop# signal will be the following. all pci[6:0] and stoppable pci_f[2,0] clocks will latch low in their next high to low transition. the pci_stop# setup time tsu is 10 ns, for transitions to be recognized by the next risin g edge. pci_stop# pci_f[2:0] 33mhz pci[6:0] 33mhz tsu assertion of pci_stop# waveforms pci_stop# - assertion (transition from logic "1" to logic "0") cpu_stop# cput cpuc the impact of asserting the cpu_stop# pin is all cpu outputs that are set in the i 2 c configuration to be stoppable via assertion of cpu_stop# are to be stopped after their next transition following the two cpu clock edge sampling as shown. the final state of the stopped cpu signals is cput=high and cpuc=low. there is to be no change to the output drive current values. the cput will be driven high with a current value equal to (multsel0) x (i ref), the cpuc signal will not be driven. cpu_stop# - assertion (transition from logic "1" to logic "0") assertion of cpu_stop# waveforms cpu_stop# functionality # p o t s _ u p ct u p cc u p c 1l a m r o nl a m r o n 0t l u m * f e r it a o l f
19 integrated circuit systems, inc. ics950211 0465e?05/17/05 ordering information ics950211 y flf-t min max min max a2.412.80.095.110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c0.130.25.005.010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h0.380.64.015.025 l0.501.02.020.040 n 0 8 0 8 min max min max 56 18.31 18.55 .720 .730 10- 0034 reference doc.: jedec publi cation 95, m o-118 variations see variations see variations n d mm. d (inch) see variations see variations 0.635 basic 0.025 basic symbol in millimeters in inches common dimensions common dimensions index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package example: designation for tape and reel packaging rohs compliant package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y f lf- t
20 integrated circuit systems, inc. ics950211 0465e?05/17/05 ordering information ics950211 y glf-t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c 240 mil tssop package example: designation for tape and reel packaging rohs compliant package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y g lf- t min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a0808 aaa -- 0.10 -- .004 variations min max min max 56 13.90 14.10 .547 .555 10-0039 56-lead 6.10 mm. bod y , 0.50 mm. pitch tssop (240 mil) (20 mil) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153
21 integrated circuit systems, inc. ics950211 0465e?05/17/05 revision history rev. issue date description page # e 5/17/2005 1. updated description on byte 13. 2. updated lf ordering information from "lead free" to "rohs compliant". 9,19-20

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